Senior Digital Verification Engineer

Samsung Israel Research Center (SIRC) is shaping the world of tomorrow, today. Focusing beyond the horizon and pushing exciting developments in many key areas of technology. Samsung is creating a new era of continuous innovation, bringing value and contribution to society and creating a workplace where our employees can enjoy making the most of their talent, creativity and passion.

Samsung R&D Center is looking for Senior Digital Verification Engineer to join our Memory team!

Join the cutting-edge team at Samsung R&D Center as we embark on shaping the future of technology today.

The Group

The R&D center is part of Samsung’s world-leading Flash memory division, which is responsible for developing and manufacturing SSD, eMMC/UFS, and emerging memory products.

The center conducts research and development of signal processing algorithms and system architecture for Samsung’s next generation platforms.

The center includes experienced researchers in the fields of machine learning, signal processing, error correction codes, encryption and data security.

We offer the candidates a unique opportunity for personal development.

· Work with innovative and top caliber memory experts in a collegial and fun environment.

· Work on challenging and innovative solutions for cutting-edge hardware of Samsung world-class memory products.

· Work in a dynamic team that provides continuous opportunities for learning and growth.

What will you do?

· Responsible for the full life cycle of verification, from verification planning to test execution and coverage closure.

· Plan the verification of complex digital IPs, by fully understanding the design specification and collaborate closely with design and algorithm engineers to identify important verification scenarios.

· Architect and develop robust verification environments from scratch.

· Debug tests with design engineers to deliver functionally correct blocks.

Requirements

• BSc in Electrical Engineering or Computer Engineering from leading university.
• At least 5 years of hands on experience in VLSI verification.
• Hands-on expertise in SystemVerilog and UVM

Developed verification environments\ Methodological approach to the verification tasks planning and execution\ Scripting skills in Python

Advantages

• Experience with Linux/Unix environments
• Experience with Cadence tools such as Xcelium, vManager, and Indago.